The present invention relates to a binary adder for calculating the sum of two operands, among which one of the operands has a fixed, known value.
The invention also relates to a parallel-serial binary multiplier for calculating the product between a serial operand having a random binary value and a parallel operand having a fixed, known binary value.
Adders and multipliers are operators used in most information processing systems from microprocessors up to complete computers. Multipliers are often the critical operators of an information processing system, both from the standpoint of their speed and from the standpoint of the material cost involved in the realization thereof.
The situation arises that one of the operands is not only fixed, but also known at the time of realizing the operator. This is particularly frequent in the field of specialized integrated circuits specifically designed for effecting a particular algorithm. Particular reference is made to signal processing algorithms. For example, in the field of image signal transmission, the image signal undergoes a compression and coding treatment prior to its transmission.
This particularly includes a linear transformation, such as a discrete cosine transform. Such a transformation is conventionally represented by a graph, in which the branches represent a multiplication operation and the nodes an addition or subtraction operation.
Such graphs are described in "A fast computational algorithm for the discrete cosine transform" by W.H. CHEN et al, IEEE Transactions on Communications, vol. COM-25, No. 9, September 1977, pp 1004 to 1009, "A high FDCT processor for real-time processing of NTSC colot TV signal" by A. JALALI et al, IEEE Transactions on Electromagnetic Compatibility, vol. EMC-24, No. 2, May 1982, pp 278 to 286 and U.S. Pat. No. 4,385,363.
In such a linear transformation, each multiplication operation relates to a known operand, whose binary value is of a random nature, and a fixed operand, whose binary value is known.
In the prior art circuits, the fact that one of the operands is fixed and known is not taken into account. Although one of the two operands to be added or multiplied is fixed, use is generally made of a complete multiplier or adder making it possible to deal with two operands having a random value. This is not satisfactory. Thus, advantages could be obtained if account was taken of the fact that one of the two operands is fixed. These advantages consist of a higher operator calculating speed or a reduction in the surface occupied by the operator on an integrated circuit.
It could clearly be envisaged to force one of the inputs of the operator to the value of the fixed operand by linking the different bits with adequate potentials. However, there would only be small speed and surface gains.
A known solution taking account of the fact that one of the two operands is fixed is storage in a read only memory of the precalculated results of the operation between said fixed operand and all the possible values of the variable operand. The operation then amounts to reading into a read only memory, the variable operand serving as an index for addressing said memory.
This method can have a certain interest for some applications. However, these applications are limited, because the size of the read only memory and the access time thereto increase very rapidly with the size of the operands. The very significant size of the ROM in particular makes it impossible to use such a method for producing adders or multipliers in the form of integrated circuits, because the surface cost is excessive.
The prior art addition or multiplication operators are consequently not very fast and are expensive as regards surface in the case of an integrated construction, no matter whether they are in the form of a standard multiplier being able to multiply two variable operands or in the form of a table contained in a ROM.